21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011, Madrid, İspanya, 26 - 29 Eylül 2011, cilt.6951 LNCS, ss.1-10
Exploration of energy & delay trade-offs requires a sizing solution for minimal energy under operating delay and output load constraints. In this work, a simple method called Constant Stage Effort Ratio (CSER) is proposed for minimal energy solution of digital circuits with a given target delay. The proposed method has a linear run-time dependence on the number of logic gates that is exponential for the optimal solution. As sample cases, the proposed algorithm is applied to parallel VLSI adders with varying bit-widths at 65nm CMOS technology. CSER sizing algorithm provides more than 300x run-time improvement compared to energy optimal solution with a worst case difference of 10% in energy for a 128-bits Kogge-Stone adder. © 2011 Springer-Verlag.