M. Aktan Et Al. , "A quick method for energy optimized gate sizing of digital circuits," 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011 , vol.6951 LNCS, Madrid, Spain, pp.1-10, 2011
Aktan, M. Et Al. 2011. A quick method for energy optimized gate sizing of digital circuits. 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011 , (Madrid, Spain), 1-10.
Aktan, M., Baran, D., & Oklobdzija, V. G., (2011). A quick method for energy optimized gate sizing of digital circuits . 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011 (pp.1-10). Madrid, Spain
Aktan, Mustafa, Dursun Baran, And Vojin G. Oklobdzija. "A quick method for energy optimized gate sizing of digital circuits," 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011, Madrid, Spain, 2011
Aktan, Mustafa Et Al. "A quick method for energy optimized gate sizing of digital circuits." 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011 , Madrid, Spain, pp.1-10, 2011
Aktan, M. Baran, D. And Oklobdzija, V. G. (2011) . "A quick method for energy optimized gate sizing of digital circuits." 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011 , Madrid, Spain, pp.1-10.
@conferencepaper{conferencepaper, author={Mustafa AKTAN Et Al. }, title={A quick method for energy optimized gate sizing of digital circuits}, congress name={21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011}, city={Madrid}, country={Spain}, year={2011}, pages={1-10} }