Design of digital filters for low power applications using integer quadratic programming

Aktan M., Dündar G.

15th International Workshop on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, PATMOS 2005, Leuven, Belgium, 20 - 23 September 2005, vol.3728 LNCS, pp.137-145, (Full Text) identifier

  • Publication Type: Conference Paper / Full Text
  • Volume: 3728 LNCS
  • Doi Number: 10.1007/11556930_15
  • City: Leuven
  • Country: Belgium
  • Page Numbers: pp.137-145
  • Istanbul Medipol University Affiliated: No

Abstract

An integer quadratic programming based formulation is proposed for the design of FIR filters implemented on Digital Signal Processors (DSP). The method unifies the cost of switching activity and number of ones in coefficients and is applicable to DSPs having multiple multiply accumulate units. Four FIR filter examples are designed with the proposed method. Power simulation results show that up to 38% power reduction can be achieved in the multiply accumulate unit of a DSP using the optimized coefficients. The resulting coefficients show better performance than coefficients optimized with previously proposed methods such as reordering coefficients. © Springer-Verlag Berlin Heidelberg 2005.