An alternative carry-save arithmetic for new generation field programmable gate arrays


ÇIni U., Aktan M., Morgül A.

Turkish Journal of Electrical Engineering and Computer Sciences, vol.24, no.2, pp.435-447, 2016 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 24 Issue: 2
  • Publication Date: 2016
  • Doi Number: 10.3906/elk-1306-184
  • Journal Name: Turkish Journal of Electrical Engineering and Computer Sciences
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus, TR DİZİN (ULAKBİM)
  • Page Numbers: pp.435-447
  • Keywords: Digital arithmetic, redundant numbers, FPGA, FIR filters
  • Istanbul Medipol University Affiliated: No

Abstract

In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAS). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than conventional binary multiply-add implementations.