Energy efficient implementation of parallel CMOS multipliers with improved compressors

Baran D., Aktan M., Oklobdzija V. G.

16th ACM/IEEE International Symposium on Low-Power Electronics and Design, ISLPED'10, Austin, TX, United States Of America, 18 - 20 August 2010, pp.147-152, (Full Text) identifier

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1145/1840845.1840876
  • City: Austin, TX
  • Country: United States Of America
  • Page Numbers: pp.147-152
  • Keywords: Arithmetic and logic structures, Booth encoding, High-speed arithmetic, Low-power design, VLSI
  • Istanbul Medipol University Affiliated: No

Abstract

Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16×16-bit Booth and Non-Booth multipliers are analyzed in energy and delay space under varying constraints. It is shown that Non-Booth multipliers start to become more energy e±cient for strict delay targets. In addition, novel 3:2 and 4:2 compressors are presented to save energy at the same target delay. The proposed compressors provide up to 20% energy reduction depending on the target delay at 65nm CMOS technology. Non-Booth multiplier implemented with the proposed compressors provides performance advantage as the voltage is scaled from its nominal value. Further, we examined all designs in 45nm, 32nm and 22nm CMOS technology nodes. © 2010 ACM.