Optimal transistor sizing and voltage scaling for minimal energy use at fixed performance

Oklobdzija V. G., Aktan M., Baran D.

7th Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2012, Cordoba, Argentina, 4 - 12 August 2012, pp.1-10 identifier

  • Publication Type: Conference Paper / Full Text
  • City: Cordoba
  • Country: Argentina
  • Page Numbers: pp.1-10
  • Keywords: Design Methodology, Digital Circuit Optimization, Digital Integrated Circuits, Integrated Circuits Modeling, Integrated Circuits Synthesis, Low Power Design, Transistor Sizing, Very Large Scale of Integration
  • Istanbul Medipol University Affiliated: No


This paper presents a simple sizing method for low-power that is comparable in speed and simplicity to the Logical Effort sizing. Yet, the accuracy of the results is in the range of simulation errors. The method is two orders of magnitude faster than methods based on convex optimization, allowing to make quick design choices and architectural trade-offs. In the standard cell environment the method can reduce power by more than 30% over existing designs obtained using synthesis tools. These results are confirmed on examples implemented in 45nm process. © 2012 EDIUNS.